Test program development in VLSI testing

Pao Yue-kong Library Electronic Theses Database

Test program development in VLSI testing


Author: Cheung, Kam-tim
Title: Test program development in VLSI testing
Degree: M.Sc.
Year: 1996
Subject: Integrated circuits -- Very large scale integration -- Testing
Hong Kong Polytechnic University -- Dissertations
Department: Multi-disciplinary Studies
Pages: ix, 162 leaves : ill. ; 30 cm
Language: English
InnoPac Record: http://library.polyu.edu.hk/record=b1235558
URI: http://theses.lib.polyu.edu.hk/handle/200/1166
Abstract: This dissertation describes the philosophies of simulation post-processing, which includes the approaches of integrating design and test, the evolution of simulation post-processors, the concept of independent database, the electronic design interchange format, the test specification format, the concept of timeplate synthesis, the methodologies of test program generation, and the problems associated with simulation post-processing. It describes how an automatic test program generation environment was developed by making use of the Summit Design's TDS software modules as the building blocks. A new design-to-test process flow is defined. Each portion in the system is described, which includes converting the simulation output file into TDS's independent database, combining the best-case and worst-case timing of simulation patterns, checking simulation rules, conditioning stimulus, performing timeplate synthesis, generating test program for the target tester, and preparing simulation file from the post-processed database for re-simulation and fault simulation. A solution of eliminating conversion errors of simulation post-processing is also proposed. In this approach, a functional test program can be generated within minutes, which dramatically shortens the test program development time and gets a new product faster to market. Two case studies were performed to evaluate and demonstrate the efficiency and the effectiveness of the approach. The first case study made use of two system-level simulation patterns with the Verilog logic simulation Value Change Dump file format. The second case study was performed via a chip-level simulation pattern with the QuickSim logic simulator Logfile format. The target ATE tester was the Teradyne A580 tester.

Files in this item

Files Size Format
b12355586.pdf 6.720Mb PDF
Copyright Undertaking
As a bona fide Library user, I declare that:
  1. I will abide by the rules and legal ordinances governing copyright regarding the use of the Database.
  2. I will use the Database for the purpose of my research or private study only and not for circulation or further reproduction or any other purpose.
  3. I agree to indemnify and hold the University harmless from and against any loss, damage, cost, liability or expenses arising from copyright infringement or unauthorized usage.
By downloading any item(s) listed above, you acknowledge that you have read and understood the copyright undertaking as stated above, and agree to be bound by all of its terms.


Quick Search


More Information