The implementation of random sampling, oversampling and undersampling systems

Pao Yue-kong Library Electronic Theses Database

The implementation of random sampling, oversampling and undersampling systems

 

Author: Cheng, Sing-yee
Title: The implementation of random sampling, oversampling and undersampling systems
Degree: M.Sc.
Year: 1996
Subject: Signal processing -- Digital techniques
Sampling (Statistics)
Hong Kong Polytechnic University -- Dissertations
Department: Multi-disciplinary Studies
Pages: 83 leaves : ill. ; 30 cm
Language: English
InnoPac Record: http://library.polyu.edu.hk/record=b1234955
URI: http://theses.lib.polyu.edu.hk/handle/200/2206
Abstract: In Digital Signal Processing (DSP), sampling process looks like a simple operation for converting an analog signal into a digital signal. However, different sampling processes, which are random sampling, oversampling and undersampling, have their own properties. These properties will be investigated first in this dissertation and then their special applications will be suggested. In random sampling, the alias-free property solves the limitation of aliasing in regular sampling and further extends the baseband frequency of an input signal beyond to its Nyquist limit. In addition, a novel hybrid Additive Random Sampling (ARS), which can maintain a certain degree of randomness, is evaluated. By applying oversampling and undersampling processes, an alternative approach in designing the 16- or higher-bit A/D converter, which overcomes the limitations of linearity, manufacturing cost, temperature effect, aging and matching in conventional analog design is discussed. Both the theoretical knowledge and practical designs will be discussed. The instability of this converter will be analyzed by root locus and simulations. The feedforward and feedback structures are also suggested to improve the stability and further increase the resolutions in this application. Decimation filter is one of the kernels in the above converter. A novel architecture which can relieve the bottleneck of its filter design has been developed. Last but not the least, an numerical analysis in Application Specific Integrated Circuit (ASIC) design for minimizing the gate count in decimation filter design is suggested.

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