Supply current monitoring in mixed signal VLSI

Pao Yue-kong Library Electronic Theses Database

Supply current monitoring in mixed signal VLSI

 

Author: Yu, Ming-fai Alex
Title: Supply current monitoring in mixed signal VLSI
Degree: M.Sc.
Year: 2000
Subject: Integrated circuits -- Very large scale integration
Electric currents
Hong Kong Polytechnic University -- Dissertations
Department: Multi-disciplinary Studies
Dept. of Electronic and Information Engineering
Pages: iii, 82 leaves : ill. ; 30 cm
Language: English
InnoPac Record: http://library.polyu.edu.hk/record=b1517760
URI: http://theses.lib.polyu.edu.hk/handle/200/2447
Abstract: The requirements on quality and reliability of semiconductors have been emphasized since 1980s; this is especially driven by the auto industry. Heading into 1990s, the accepted failure rates have been in the range from 1000 dpm to 50 dpm and will be declined in the years ahead. In future, it is necessary to lower the failure rate to less than 4 dpm in order to achieve the Zero Defects quality. The problem for semiconductor manufacturers is how to obtain zero defect level. This is a difficult goal for a standard product supplier and an incredible one for the Application Specific Integrated Circuit (ASIC) and custom IC suppliers. Conventional approaches for accomplishing these goals are: increasing test fault coverage, increasing burn-in coverage, increasing ESD awareness and developing generic qualification vehicles. While these methods are making great strides in quality improvement, Supply Current Monitoring (SCM) will be shown to enhance the ability to successfully achieve the desired low defect levels [1]. Supply Current Monitoring (IDDQ*) in CMOS digital ASICs was widely applied during the past decade. It is a testing method that was proved to enhance the conventional testing method [2]. This dissertation intends to discuss and study the various aspects of IDDQ testing methodology application on the mixed signal CMOS micro-controller in real life industrial environment. Employing IDDQ testing on CMOS technology, the user can obtain a product with greater reliability. These benefits will be introduced, which clearly support IDDQ implementation. The dissertation will investigate the suitability of supply current monitoring as a technique for testing of analogue circuit modules. Chapter 1 gives an introduction to IDDQ testing methodology and look at the common CMOS VLSI fault model which can be detected by IDDQ testing methodology. Chapter 2 will introduce the IDDQ testing concept and the fault coverage achieved by applying the technique in analogue circuit. Chapter 3 will introduce the Motorola 8-bit MCU (LU32) is to be used as a testing target to evaluate the IDDQ testing methodology. Chapter 4, a real life case study will be taken to show how the IDDQ testing methodology is applied to test a 8-bit micro-processor with mixed signal modules embedded. A Motorola 8-bit MCU will be used as a testing target in the dissertation. Chapter 5 utilizes the information given in Chapter 4 to examine the feasibility of IDDQ testing in the IC production line based on economic issues. A guideline for the cost-benefit analysis is given to decide whether or not IDDQ testing will result in profit for a particular production line. Chapter 6 summarizes the main concepts and also provides precautionary suggestions and guidelines for using IDDQ testing.

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