Integrated on-chip inductors for radio frequency CMOS circuits

Pao Yue-kong Library Electronic Theses Database

Integrated on-chip inductors for radio frequency CMOS circuits


Author: Tsui, Chiu
Title: Integrated on-chip inductors for radio frequency CMOS circuits
Degree: M.Phil.
Year: 2004
Subject: Hong Kong Polytechnic University -- Dissertations
Metal oxide semiconductors, Complementary
Radio frequency
Electric inductors
Integrated circuits
Department: Dept. of Electronic and Information Engineering
Pages: 1 v. (various pagings) : ill. ; 30 cm
Language: English
InnoPac Record:
Abstract: The project is concerned with the study of integrated on-chip inductors for RF CMOS circuits. On-chip inductors were fabricated and characterized using standard 0.6um CMOS process with 3 metal layers. The research is targeted on the optimization of on-chip inductors by varying the layout parameters including metal width, metal layer topology and number of turns. Planar (1 metal layer), 3D (3 metal layers) and stacked (2 metal layers) inductor structures were investigated. The scattering parameters of the samples were measured by a network analyzer up to 10 GHz. The effective resistance, effective inductance and quality factor were then extracted from the S parameters. The results were verified by numerical simulation with MicroWave Office software. Simulation was used to study the performance of the samples after the Si substrate was removed by etching. Our results show that inductors with different metal widths have optimum Q factor at different operation frequencies. The inductor with wider metal width benefits at lower frequencies. On the other hand, the inductor with narrower metal width has comparatively lower effective resistance at higher frequencies. This is the consequence of combined skin and proximity effects in the metal lines and the eddy current loss in the substrate. In addition, it is found that after the substrate removal the planar inductor has the largest improvement in Q factor. The proximity effect from adjacent metal layers limits the performance of the 3D and stacked back-etched inductors as compared with the planar inductor. Different topologies of the 2-layer stacked inductors have been studied. The result proves that the proximity effect from adjacent metal layers acts as a major loss affecting the Q factor of this type of inductor. Further interlayer distance leads to further increase of Q factor. Simulation shows that the substrate eddy current loss in stacked inductors plays a minor role because of the reduced size. Comparing the three types of inductors, it is found that the back-etched planar inductor has the highest Q factor. It suffers from least proximity effect from adjacent metal lines after etching of the substrate. The drawback is its large size. The 3D inductor has comparatively high Q factor as well as small inductor size. It also has the highest peak Q frequency and self-resonant frequency.

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