Study of delamination in IC packaging

Pao Yue-kong Library Electronic Theses Database

Study of delamination in IC packaging

 

Author: Tse, Kwok-fai
Title: Study of delamination in IC packaging
Degree: M.Sc.
Year: 2000
Subject: Electronic packaging
Integrated circuits
Hong Kong Polytechnic University -- Dissertations
Department: Multi-disciplinary Studies
Dept. of Applied Physics
Pages: v, 85 leaves : ill. (some col.) ; 31 cm
Language: English
InnoPac Record: http://library.polyu.edu.hk/record=b1516285
URI: http://theses.lib.polyu.edu.hk/handle/200/3747
Abstract: Delamination in the plastic Integrated Circuit (IC) industry is one of the main causes to the formation of failure. This thesis discusses the methods which will reduce such kind of failure by means of using different test methods. They are: (I) process parameter optimization on lead frame, molding compound, die attach materials and so on. (2) Plasma Cleaning method on IC surface. With the help of these verification tests (Pressure Pot test (PPOT) / Autoclave (ACLV) and Infra-red reflow (IR-reflow)), we will use them to verify the effectiveness of the tests on delamination and how they can improve the package reliability. During the test, various factors to the minimization of the cause of delamination will be used. They are: Plasma Cleaning method, new molding material, different lead frame design will be used as a variation factors in order to get maximum performance of the plastic IC packages to the formation of delamination. From this paper, the results of the performance of the different material parameters will be discussed and a thorough comparison of the different material will be presented and determined the best material parameters will be. From the above test, PPOT / ACLV will be used an introduction of the moisture penetration of the package. Temperature Cycle test (TMCL) / Thermal Shock test (TMSK) will be used as an acceleration test to the formation of delamination of the interface between mold compound and the corresponding area inside the IC packages by means by either in gas phase or in liquid phase. Solder reflow will be used as a simulation of the action of the surface mounting of the IC to the Printed Circuit Board (PCB) in which expansion of moisture will cause the expansion of the interfacial space when there is delamination found between layers. Besides, Statistical Process Control (SPC) methods will be introduced in this project in order to obtain the optimized parameter for the production of the IC packages. Therefore, a certain kind of quality control tools will be introduced. For instance, Design of Experiment (DOE) and Failure Mode and Effect Analysis (FMEA) will be employed so as to obtain these parameters.

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