Generalized RISC simulator

Pao Yue-kong Library Electronic Theses Database

Generalized RISC simulator

 

Author: Hui, Chi-kwok
Title: Generalized RISC simulator
Degree: M.Sc.
Year: 1994
Subject: Reduced instruction set computers
Hong Kong Polytechnic -- Dissertations
Department: Multi-disciplinary Studies
Pages: iv, 120 leaves : ill. ; 30 cm. + computer disk
Language: English
InnoPac Record: http://library.polyu.edu.hk/record=b1182939
URI: http://theses.lib.polyu.edu.hk/handle/200/3920
Abstract: In order to solve the problems, that is, no generalized RISC simulator and limitations of current simulators in the simulation of RISC system, a high level model of RISC simulation is defined. Its RISC description is a new pseudo language which is different from ISP and VHDL. The levels of description are organized to model RISC easily and effectively. The Motorola's RISC system is selected to evaluate the model. Correspondingly, a low level model is defined with complete low level graphic and written RISC description which includes structure, behaviour, timing and interconnection. One simulating tool is designed and implemented. It interprets RISC description, behaves as the simulator of RISC, monitors the parallelism of various execution units of the RISC, and records the execution and status in the RISC pipeline with details. Each simulation processes only behaviour of structure with any signal arrival for the timing specified. Various simulator features are included except that break point is replaced by adjustable step. The state of simulation can be saved and resumed later. The RISC II is selected to test the simulating tool with a manually compiled simple multiplication program. The Digital's Alpha architecture RISC processor is selected to test the high level pseudo language description. At last, the ability of the pseudo language to describe generalized CISC processor is tested by a typical architecture of CISC processor.

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