Design of pass-transistor CMOS adiabatic logic and its application

Pao Yue-kong Library Electronic Theses Database

Design of pass-transistor CMOS adiabatic logic and its application


Author: Tong, Kin-chung
Title: Design of pass-transistor CMOS adiabatic logic and its application
Degree: M.Sc.
Year: 2000
Subject: Metal oxide semiconductors, Complementary -- Design and construction -- Data processing
Low voltage integrated circuits -- Design and construction -- Data processing
Digital integrated circuits -- Design and construction -- Data processing
Hong Kong Polytechnic University -- Dissertations
Department: Multi-disciplinary Studies
Dept. of Electronic and Information Engineering
Pages: x, 165 leaves : ill. ; 30 cm
Language: English
InnoPac Record:
Abstract: Low-power design is a major research field in recent years. To achieve low power consumption in digital systems, various of methods can be adapted, such as the proper choice of circuit design, reduction of the voltage swing and clocking strategies can be used to reduce power dissipation at the transistor level. Now, many research efforts are put into the reduction of power dissipation by using adiabatic concept and theory. The design of Pass-transistor Adiabatic Logic (PAL) circuit is one of these approaches. The PAL acts as a switch to allow the signal energies stored on the circuit capacitors recycled instead of dissipated as heat during the charging and discharging cycle. The basic objective of this project is to evaluate the energy consumption of the Pass-transistor Adiabatic Logic circuit and its applicability. 3 different types of full adders, CMOS, Complementary Pass-transistor Logic (CPL) and nMOS PAL, are simulated to prove that the PAL has a better performance than the others in terms of power saving. Then, 2 different types of arithmetic Logic Units (ALU), nMOS ALU and CPL ALU, are designed with PAL implementation and simulate. The simulation result shows that the PAL can be implemented into a more complicate logic, such as CPU. However, errors will occur as the nMOS PAL ALU operate up to 16MHz with power clock at 64MHz, while the CPL PAL ALU can operate up to 32MHz without error with PC at 128MHz. This is because different type of logic design will have different delay and the PAL design is very sensitive to the gate delay. On the other hand, the PAL will introduce one PC period delay between stage-to-stage interconnection. This will degrade the system operation frequency significantly, especially for a complicate system. The simulation results show that the PAL technique can be implemented into a complex electronic system such as ALU. But, it must consider the trade-offs between the operation frequency and power consumption when implement the PAL into the electronic system.

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