Cost effective image compression/decompression and VLSI implementation

Pao Yue-kong Library Electronic Theses Database

Cost effective image compression/decompression and VLSI implementation

 

Author: Tu, Chak-ming
Title: Cost effective image compression/decompression and VLSI implementation
Degree: M.Sc.
Year: 1994
Subject: Image compression -- Cost effectiveness
Coding theory
Integrated circuits -- Very large scale integration -- Design and construction
Image processing -- Digital techniques
Hong Kong Polytechnic -- Dissertations
Department: Multi-disciplinary Studies
Pages: 90, [95] leaves : ill. ; 30 cm
Language: English
InnoPac Record: http://library.polyu.edu.hk/record=b1182933
URI: http://theses.lib.polyu.edu.hk/handle/200/5304
Abstract: Data compression is the reduction of redundancy in data representation in order to decrease storage and communication costs. Most researches of still picture compression were performed on continuous-tone imagery and standard was emerged, such as JPEG. However, these comprehensive techniques may not be best suited to the computer-generated imageries. Actually, this kind of imageries possesses high redundancy which can be compressed in a high efficiency and decompressed losslessly. In this dissertation, a new compression methodology, called Modified Huffman plus Run-length Coding, is developed. This methodology is taking the advantages of the nature of computer-generated imaginery. As being specifically designed for handling this kind of imageries, this technique can achieve a considerably high compression ratio (average compression ratio is 3.33 :1). Data compression techniques have been widely used in practice primarily through software implementations which, however, cannot meet the speed and performance requirements of current and future systems. In this dissertation, the decompression methodology is implemented in a VLSI design. Compressed data is preloaded to the ROM and through this VLSI, decompressed data will then be outputted to video RAM for displaying the graphics. High efficiency does not imply complicated hardware implementation. The proposed hardware algorithms exploit the principles of parallelism and integration in order to obtain high speed and throughput. The hardware design is realized by VHSIC HDL (Very-High Speed Integrated Circuit Hardware Description Language) or VHDL in short, through the tools of Synopsys and WorkView. The design considerations include the scan test for checking the product quality in production. In this dissertation, the scan test results indicate that this test can be economic (without inserting too many dummy logics in order to achieve a high fault coverage rate) if precautions are taken in the design stage. Finally, the VLSI design layout is generated. This VLSI design of 3098 gates effectively decompresses the images 'on-the-fly' in less than 0.1 second. Even though this design is housed in a 44-pin package, it can be integrated with another video processing units like sprite processor and DMA to form an effective system for generating moving pictures. This VLSI can be applied to the video display portion of electronic equipments such as video games and CD-G.

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