Implementation of Cyclic-Layered QC-LDPC decoder on FPGA

Pao Yue-kong Library Electronic Theses Database

Implementation of Cyclic-Layered QC-LDPC decoder on FPGA

 

Author: Fan, Jianfeng
Title: Implementation of Cyclic-Layered QC-LDPC decoder on FPGA
Degree: M.Sc.
Year: 2013
Subject: Error-correcting codes (Information theory)
Signal processing.
Hong Kong Polytechnic University -- Dissertations
Department: Faculty of Engineering
Pages: viii, 80 leaves : ill. (some col.) ; 30 cm.
Language: English
InnoPac Record: http://library.polyu.edu.hk/record=b2643475
URI: http://theses.lib.polyu.edu.hk/handle/200/7126
Abstract: Channel codes which are most popular widely used in error-control technique. Among of the channel codes, Low-Density Parity-check Codes (LDPC) are one of the powerful channel codes which were first introduced in 1963. LDPC codes are widely used in the communication systems, such as video-broadcasting, satellite communication that are being considered the most efficient forward-error-correction codes. In this thesis, the Quasi-cyclic Low-Density Parity-Codes (QC-LDPC) is considered as the channel code which is implemented into the decoding due to its parity-check matrix is the shifted identity matrix. The modified cyclic-layered decoding algorithm is used for decoding QC-LDPC which is easier to be applied in the hardware platform. Cause any software environment using the Central Processing Unit (CPU), such as c/c + +, is very time-consuming for the long length codeword. Aiming to generate the error performance of the QC-LDPC, We use the VHSIC Hardware Description Language (VHDL) as the code description of the whole design. Hence, the decoding platform of the QC-LDPC is implemented in the Stratix IV EP4SE530H35 FPGA environment.

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