Architecture design of QC-LDPC decoder with cyclicly-coupled codes

Pao Yue-kong Library Electronic Theses Database

Architecture design of QC-LDPC decoder with cyclicly-coupled codes


Author: Lu, Qing
Title: Architecture design of QC-LDPC decoder with cyclicly-coupled codes
Degree: M.Sc.
Year: 2014
Subject: Signal processing.
Error-correcting codes (Information theory)
Hong Kong Polytechnic University -- Dissertations
Department: Faculty of Engineering
Pages: xi, 78 leaves : illustrations ; 30 cm
Language: English
InnoPac Record:
Abstract: Out of the need for a superb forward error correction (FEC) scheme, the well known low-density parity-check (LDPC) codes arouse our interest. With Belief Propagation (BP) decoding, this class of channel codes demonstrates a limit-approaching ability but implementation issues remain. This thesis focus-es on designing a decoder architecture with excellent error performance, high throughput and low complexity. In this work, a sub-class of LDPC codesquasi-cyclic LDPC (QC-LDPC) codesis investigated and decoded with quantized sum-product algorithm (SPA). An optimized RAM-based decoder architecture with extraordinary performance is proposed. Considering the implementation issues, codes with cyclicly coupled structure are proposed. At the cost of a slight increase in architectural redundancy, the decoders for these codes achieve a significant improvement in bit error rate (BER). The proposed architecture has been implemented onto a field programmable gate array (FPGA) for a 98304-bit 5/6-rate cyclicly-coupled QC-LDPC (CC-QC-LDPC) code. The experimental results show no error floor above a BER of 10¹⁴. As the bit-energy-to-noise power-spectral-density ratio (Eb/N0) goes up to 3.50 dB, no errors are detected among the 1.14 × 10¹⁶ decoded bits. Besides, the architectural throughput of our implementation is up to 1.9 Gbps at a clock rate of 100 MHz.

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