A study of fault detection problems in self checking circuits

Pao Yue-kong Library Electronic Theses Database

A study of fault detection problems in self checking circuits

 

Author: Pang, Cho-wai Joseph
Title: A study of fault detection problems in self checking circuits
Degree: M.Phil.
Year: 1997
Subject: Automatic checkout equipment
Hong Kong Polytechnic University -- Dissertations
Department: Dept. of Electronic Engineering
Pages: x, 113 leaves : ill. ; 30 cm
Language: English
InnoPac Record: http://library.polyu.edu.hk/record=b1420177
URI: http://theses.lib.polyu.edu.hk/handle/200/835
Abstract: The problems of self-checking circuits under different fault models such as multiple fault, open and bridging fault models were thoroughly examined and addressed. Various test generation and design-for-testability methods were investigated in order to find efficient solutions to tackle the problems. In particular, the following were achieved: - The multiple stuck-at fault coverage problem was addressed. Off-line multiple stuck-at fault detection method was studied. In this study, a multiple stuck-at fault detection algorithm was developed for two-rail and parity checkers. The algorithm has been proved to achieve 100% multiple stuck-at fault coverage and requires less test vectors comparing to previously proposed method. - The open and bridging fault coverage problems in CMOS circuits were studied, with particular emphasis on the bridging fault detection problem. Stuck-at fault model is insufficient and inadequate to model bridging faults in CMOS circuits. The detection of bridging faults by voltage testing is a very complicated task. We integrated the Iddq testing technique in the self-checking system and applied the test generation method to the two-rail checkers for bridging fault detection. By combining the multiple stuck-at fault detection and Iddq testing, the test quality can be greatly increased. - The structures of domino-CMOS logic circuits are more testable than their static family for transistor stuck-open and stuck-on faults. However, the dynamic nature of the domino circuit structure prevents effective application of Iddq testing. Modification of domino-CMOS logic circuits was proposed to enhance the overall testability of both voltage and Iddq testing. Furthermore, the extra cost of hardware is also very low. - Another serious problem of the self-checking circuits is the misinterpretation of the output of the functional block due to the effect of bridging fault. In our earlier work, we focused on the use of built-in current sensor to detect bridging faults. However, Iddq testing is relatively slow in detection speed and suffers from low current resolution. The detection problem is mainly due to the occurrence of intermediate voltage at the fault site. In this respect, a sensing circuit called built-in intermediate voltage sensor(BIVS) was proposed to detect the intermediate voltage. Detailed analysis shows that the sensing circuit can achieve the self-checking requirements. So that it is suitable for on-line testing applications. An integration of BIVS and self-checking system is further proposed as an application example.

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