Systematic study of a new family of switched-resistor-circuit-based ripple estimation/cancellation methods for fast-response PFC pre-regulator

Pao Yue-kong Library Electronic Theses Database

Systematic study of a new family of switched-resistor-circuit-based ripple estimation/cancellation methods for fast-response PFC pre-regulator

 

Author: Leung, Ka Hei
Title: Systematic study of a new family of switched-resistor-circuit-based ripple estimation/cancellation methods for fast-response PFC pre-regulator
Degree: M.Phil.
Year: 2016
Subject: Electric current converters.
Electric power factor.
Hong Kong Polytechnic University -- Dissertations
Department: Dept. of Electronic and Information Engineering
Pages: xxix, 147 pages : color illustrations
Language: English
InnoPac Record: http://library.polyu.edu.hk/record=b2898256
URI: http://theses.lib.polyu.edu.hk/handle/200/8548
Abstract: Power Factor Correction (PFC) pre-regulator has been widely used for converting ac power into dc power for the consumption of mains-connected dc loads while limiting the amount of current harmonics being injected to the mains. Typically, its control circuitry consists of an inner current control loop and an outer voltage control loop. The bandwidth of the inner current control loop is typically configured to be large, which causes the input current of PFC pre-regulator to closely track the reference signal generated by the outer voltage loop. For the outer voltage loop, which regulates the average output voltage of PFC pre-regulator, a narrow bandwidth is commonly utilized in order to significantly attenuate the sampled double-line frequency component. Such a two-loop configuration leads to high power factor and input current with extremely low THD. However, the resultant narrow bandwidth also gives rise to poor dynamic response of PFC pre-regulator. Various methods have been proposed to achieve high power factor and fast dynamic response simultaneously. One of the well-developed strategies is the ripple cancellation approach. The main idea of this approach is that the double-line frequency component that exists in the sampled output voltage is eliminated by subtracting a replica of the sampled output voltage ripple from the actual one to generate a ripple-free signal to be further processed by the voltage error amplifier. As a result, an undistorted and sinusoidal input current can be obtained even if the bandwidth of the voltage error amplifier is increased considerably compared to conventional design.
By comparing the graphical representation of the actual PFC pre-regulator's output voltage with that of the idealized output voltage's equation, it is shown that the output voltage ripple does not match the description of the idealized equation when a PFC pre-regulator operates outside certain range of operating conditions. In view of this, a new ripple estimation network consisting of an amplitude tuner and a phase shifter is proposed for generating an ideal replica of the sampled output voltage ripple. The proposed amplitude tuner and phase shifter are derived from switched-resistor circuits with adjustable gain and phase angle realized by controlling the duty cycle of the switched-resistor circuits. The proposed ripple estimation network is tested by implementing it on a boost PFC pre-regulator. It is shown that the proposed ripple estimation network provides an accurate ripple estimation/cancellation over a wide range of operating conditions, thus producing minimum global cancellation error, and consistently gives rise to near-unity power factor and fast dynamic response of PFC pre-regulator under these conditions. Considering the complexity of the precise ripple estimation network proposed above, its circuitry is simplified as inferred from the main figures of merit of PFC pre-regulator under the action of ripple cancellation. Another ripple estimation method is suggested to minimize the local (instead of global) cancellation error, which is derived and found to be a function of the phase difference between the sampled and the estimated output voltage ripple signal. The simplified ripple estimation network is verified experimentally on a boost PFC pre-regulator. It is demonstrated that under this method the estimated output voltage ripple is consistently operated at its optimum amplitude that gives rise to the minimum local cancellation error in the presence of phase estimation error. This method also results in high power factor and low THD of PFC pre-regulator's input current. Finally, the last and the simplest ripple estimation method is developed by simply equalizing the amplitudes of the sampled and estimated output voltage ripples and imposing a constant phase angle to the estimated signal. The performances of these three proposed ripple estimation/cancellation methods are investigated and compared by implementing them on the same boost PFC pre-regulator power stage. By comparing the experimentally measured figures of merit, it is shown that the first method provides the most precise ripple estimation/cancellation which leads to near-unity power factor over a wide range of operating conditions, while the simplest method provides an economical solution for achieving high (but not unity) power factor and fast dynamic response of PFC pre-regulator.

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