| Author: | Liu, Duo |
| Title: | Write-activity-aware NAND flash memory management for PCM-based embedded systems |
| Degree: | Ph.D. |
| Year: | 2012 |
| Subject: | Embedded computer systems -- Design and construction. Flash memories (Computers) Phase change memory. Hong Kong Polytechnic University -- Dissertations |
| Department: | Department of Computing |
| Pages: | xvi, 119 p. : ill. ; 30 cm. |
| Language: | English |
| Abstract: | Due to its properties of high density, in-place update, and low standby power, phase change memory (PCM) becomes a promising main memory alternative in embedded systems, and is recently introduced to embedded system designs. However, the endurance of PCM keeps drifting down and greatly limits the lifetime of the whole system. On the other hand, NAND flash memory is widely used as a secondary storage and has been integrated into PCM-based embedded systems. So this thesis targets at an embedded system with PCM and NAND flash memory. Since both NAND flash memory and PCM have limited lifetime, how to effectively manage NAND flash memory while considering PCM endurance is a challenge issue for PCM-based embedded systems. To manage NAND flash memory, flash translation layer (FTL) is designed to emulate NAND flash memory as a disk drive, by mapping logical addresses to physical addresses in NAND flash memory at a granularity of page-level or block-level [37, 51]. Correspondingly, most of the proposed FTL techniques are mainly categorized into page-level or block-level based on the granularity of mapping unit [19]. As PCM-based main memory exhibits non-volatility feature, to obtain high access performance, FTL mapping table can be kept into PCM permanently without considering power failure. However, the frequently updated FTL mapping table imposes a large number of write activities in PCM, and may lead to a shortened PCM lifetime. Therefore, effective management techniques are needed to explore traditional page-level or block-level FTL designs and make them write activity aware, for enhancing the lifetime of the PCM-based embedded systems. In this thesis, we focus on exploring the challenge issues imposed by the management of NAND flash memory in PCM-based embedded systems. Corresponds to the existing page-level and block-level FTL designs, we present for the first time three write-activity-aware flash memory management techniques, to effectively manage NAND flash memory and enhance the lifetime of PCM-based embedded systems. To the best of our knowledge, this is the first work to study how to effectively manage NAND flash memory in PCM-based embedded systems by considering the endurance issue of PCM. We hope this work can serve as a first step towards the design of write-activity-aware flash memory management for PCM-based embedded systems. |
| Rights: | All rights reserved |
| Access: | open access |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| b25227087.pdf | For All Users | 5.13 MB | Adobe PDF | View/Open |
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