Optimizing NAND flash memory management in resource-constrained embedded systems

Pao Yue-kong Library Electronic Theses Database

Optimizing NAND flash memory management in resource-constrained embedded systems

 

Author: Qin, Zhiwei
Title: Optimizing NAND flash memory management in resource-constrained embedded systems
Degree: Ph.D.
Year: 2013
Subject: Flash memories (Computers)
Hong Kong Polytechnic University -- Dissertations
Department: Dept. of Computing
Pages: xvi, 122 p. : ill. ; 30 cm.
Language: English
InnoPac Record: http://library.polyu.edu.hk/record=b2616022
URI: http://theses.lib.polyu.edu.hk/handle/200/6993
Abstract: NAND flash memory has been widely adopted in the design of various storage systems. The capacity of NAND flash memory chips has been increasing dramatically and has doubled about every two years. The increasing capacity of NAND flash memory poses new challenges for vendors on the system management. Moreover, with the multi-level-cell (MLC) NAND flash memory becoming the mainstream in the market for lower cost and/or large-scale storage systems, some new write constraints have been introduced into the flash memory chips. These constraints further pose big challenges for existing flash memory management techniques that were originally designed for single-level-cell (SLC) NAND flash memory. In this thesis, we investigate several challenging issues in managing flash memory storage systems for resource-constrained embedded systems. Since flash memory does not support in-place updates and needs to erase before update operations, a block-device-emulation software layer, called the flash translation layer (FTL), is designed so as to provide transparent service. FTLs manage the system with three components: address translation, garbage collection, and wear-leveling. In this thesis, we optimize the management techniques in FTLs from several aspects, including the RAM cost, garbage collection over-head, and real-time storage performance taking into consideration the limited computation resource in embedded system.
First, we focus on reducing the RAM footprint for address translation when doing the mapping from logical addresses to physical addresses. To solve this problem, we propose a demand-based block-level address mapping scheme with a two-level caching mechanism for large-scale NAND flash storage systems. Our basic idea is to store the block-level address mapping table in specific pages in flash memory and design two level caches in RAM to store the on-demand block-level address mappings. Since the entire block-level address mapping table is stored in flash memory and only the demanded address mappings are loaded into RAM, the RAM footprint can be reduced. The experimental results show that our technique can achieve a 91.68% reduction in RAM cost, while the average system response time presents an average degradation of 2.02% compared with previous work. Second, we aim to reduce the garbage collection overhead and the average system response time while hiding the new write constraints in MLC NAND flash memory. To solve this problem, we first analyze the garbage collection procedure and conclude that the valid page copy is the essential garbage collection overhead. We then propose two approaches, namely, concentrated mapping and postponed reclamation, to effectively reduce the number of valid page copies. The experimental results show that, by reducing the garbage collection overhead, our scheme can achieve a minimum reduction of 30.92% in the average system response time compared with previous work. Third, we study the problem of improving the real-time storage performance of NAND flash memory in real-time embedded systems. To obtain an upper bound for system response time, we propose a real-time flash translation layer scheme to hide the variable garbage collection by using a distributed partial garbage collection policy that enables the system to simultaneously reclaim space and serve the write requests. The experimental results show that our scheme not only improves the worst-case system response time and the average system response time, but also shows a significant reduction in RAM cost compared with previous work.

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