Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor | Multi-disciplinary Studies | en_US |
| dc.creator | Cheung, Kam-tim | - |
| dc.identifier.uri | https://theses.lib.polyu.edu.hk/handle/200/1166 | - |
| dc.language | English | en_US |
| dc.publisher | Hong Kong Polytechnic University | - |
| dc.rights | All rights reserved | en_US |
| dc.title | Test program development in VLSI testing | en_US |
| dcterms.abstract | This dissertation describes the philosophies of simulation post-processing, which includes the approaches of integrating design and test, the evolution of simulation post-processors, the concept of independent database, the electronic design interchange format, the test specification format, the concept of timeplate synthesis, the methodologies of test program generation, and the problems associated with simulation post-processing. It describes how an automatic test program generation environment was developed by making use of the Summit Design's TDS software modules as the building blocks. A new design-to-test process flow is defined. Each portion in the system is described, which includes converting the simulation output file into TDS's independent database, combining the best-case and worst-case timing of simulation patterns, checking simulation rules, conditioning stimulus, performing timeplate synthesis, generating test program for the target tester, and preparing simulation file from the post-processed database for re-simulation and fault simulation. A solution of eliminating conversion errors of simulation post-processing is also proposed. In this approach, a functional test program can be generated within minutes, which dramatically shortens the test program development time and gets a new product faster to market. Two case studies were performed to evaluate and demonstrate the efficiency and the effectiveness of the approach. The first case study made use of two system-level simulation patterns with the Verilog logic simulation Value Change Dump file format. The second case study was performed via a chip-level simulation pattern with the QuickSim logic simulator Logfile format. The target ATE tester was the Teradyne A580 tester. | en_US |
| dcterms.extent | ix, 162 leaves : ill. ; 30 cm | en_US |
| dcterms.isPartOf | PolyU Electronic Theses | en_US |
| dcterms.issued | 1996 | en_US |
| dcterms.educationalLevel | All Master | en_US |
| dcterms.educationalLevel | M.Sc. | en_US |
| dcterms.LCSH | Integrated circuits -- Very large scale integration -- Testing | en_US |
| dcterms.LCSH | Hong Kong Polytechnic University -- Dissertations | en_US |
| dcterms.accessRights | restricted access | en_US |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| b12355586.pdf | For All Users (off-campus access for PolyU Staff & Students only) | 6.56 MB | Adobe PDF | View/Open |
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