Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor | Department of Electronic Engineering | en_US |
| dc.creator | Kwan, Wai-kin | - |
| dc.identifier.uri | https://theses.lib.polyu.edu.hk/handle/200/1574 | - |
| dc.language | English | en_US |
| dc.publisher | Hong Kong Polytechnic University | - |
| dc.rights | All rights reserved | en_US |
| dc.title | Investigation of techniques to resolve contention in multi-processor systems | en_US |
| dcterms.abstract | The objective of this project is to investigate contention resolution techniques for multi-processor systems. The target systems are multi-processor systems interconnected by a shared-bus architecture. In this dissertation, a literature survey is performed on the previous work that design effective arbitration protocols for different kinds of multi-processor systems. The focus of this dissertation will be put on distributed arbiter designs. Contention occurs on bus-based multi-processor system when multiple simultaneous bus access requests arise. Typically, bus arbiters are responsible for resolving such contention. They are deemed to be important system blocks in such kind of computer system. A distributed parallel arbitration system developed for a bus-based multi-processor system has been implemented. This design is based on certain mature industrial specifications. Practical results and implementation problems have been experienced from this system. Moreover, performance simulation results are recorded and analyzed. However, most of the past designs have been found to base on similar principles and do not provided significant improvements. Therefore, a new arbitration protocol is proposed in this project as an alternative method for future designs. In addition, robust arbiter designs proposed by previous studies have been studied in this project. Modification on a current well-applied distributed arbitration protocol is proposed to support fault detection and correction mechanisms. The design is implemented using an integrated logic development tool. Functional simulation of this system is done and performance evaluation will be presented. In this dissertation, the related background knowledge, design alternatives, limitations of known approaches, implementation considerations and two new approaches will be analyzed and discussed. | en_US |
| dcterms.extent | 81, [55] p. : ill. ; 30 cm | en_US |
| dcterms.isPartOf | PolyU Electronic Theses | en_US |
| dcterms.issued | 1995 | en_US |
| dcterms.educationalLevel | All Master | en_US |
| dcterms.educationalLevel | M.Sc. | en_US |
| dcterms.LCSH | Multiprocessing (Electronic computers) | en_US |
| dcterms.LCSH | Multiprocessors | en_US |
| dcterms.LCSH | Hong Kong Polytechnic University -- Dissertations | en_US |
| dcterms.accessRights | restricted access | en_US |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| b12229192.pdf | For All Users (off-campus access for PolyU Staff & Students only) | 4 MB | Adobe PDF | View/Open |
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