Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor | Multi-disciplinary Studies | en_US |
| dc.creator | Wong, Kwong-yin | - |
| dc.identifier.uri | https://theses.lib.polyu.edu.hk/handle/200/1603 | - |
| dc.language | English | en_US |
| dc.publisher | Hong Kong Polytechnic University | - |
| dc.rights | All rights reserved | en_US |
| dc.title | On the issues of applying the hardware reduction algorithm to practical linear analog circuits | en_US |
| dcterms.abstract | A lot of studies and researches have been done on how to design fault-tolerant circuits in digital field but rarely in analog field. Actually, fault-tolerant design of analog circuits is more difficult than that of digital circuits. Abhijit Chatterjee has proposed a continuous checksums-based technique [1] that can address concurrent error detection and correction in linear analog circuits and hence the reliability of the original circuit is greatly improved. These checksums of time-varying functions are possible because the function of a linear analog circuit can be represented mathematically by a set of matrices to which checksum codes can be applied. For the purpose of an error detection, a fault is assumed to cause the value of a passive circuit component to deviate from its normal value, result in a line short or open or change the operating characteristics of the active components. If the specifying parameters of a linear analog circuit change due to a fault and the failed circuit behaves as a linear system, then error correction can be performed by compensating for the changed parameter values. Otherwise, partial correction is possible. Error detection and correction are performed by adding additional hardware to the linear analog circuit. However, hardware overhead is an important issue in the implementation of the algorithm. Ying-quan Zhou has addressed the issue and proposed an algorithm for reduction of hardware overhead in linear analog checker [2] so as to optimize the hardware required in building the linear analog checker. Nevertheless, the effectiveness, feasibility, difficulties and limitations of the algorithm in the implementation process for commonly used linear analog circuits in semiconductors' industries and electronics fields have not yet been addressed. The purpose of the dissertation is to address all these issues in the implementation of the hardware overhead reduction algorithm for linear analog checkers based on selected practical linear analog circuits. In addition, a software program will be established to implement the hardware overhead reduction algorithm by using MATLAB programming. | en_US |
| dcterms.extent | x, 139 p. : ill. ; 30 cm | en_US |
| dcterms.isPartOf | PolyU Electronic Theses | en_US |
| dcterms.issued | 1997 | en_US |
| dcterms.educationalLevel | All Master | en_US |
| dcterms.educationalLevel | M.Sc. | en_US |
| dcterms.LCSH | Electric circuits, Linear | en_US |
| dcterms.LCSH | Linear integrated circuits | en_US |
| dcterms.LCSH | Electronic circuit design | en_US |
| dcterms.LCSH | Hong Kong Polytechnic University -- Dissertations | en_US |
| dcterms.accessRights | restricted access | en_US |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| b13981006.pdf | For All Users (off-campus access for PolyU Staff & Students only) | 3.87 MB | Adobe PDF | View/Open |
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