| Author: | Tse, Ming-chi Jamin |
| Title: | ASYNMPU : a fully asynchronous microprocessor |
| Degree: | M.Phil. |
| Year: | 1999 |
| Subject: | Asynchronous circuits -- Design and construction Hong Kong Polytechnic University -- Dissertations |
| Department: | Department of Electronic and Information Engineering |
| Pages: | xvii, 149 leaves : ill. ; 31 cm |
| Language: | English |
| Abstract: | In this thesis, the design and implementation of an asynchronous 8/16 bit Microprocessor, namely, the ASYNMPU, are described. The objective of this work is to investigate whether it is possible to build commercially realistic complex circuits using an asynchronous design style and then assess the advantages that the designed circuits offer. Recently, the studies of asynchronous computer (or clockless computer) have attracted much attention in the field of computer architecture design. It is known that asynchronous design methodology with handshake protocol can avoid the clock-related timing problems by removing the global clock signal. The overall power dissipation can be reduced potentially since functional units are active only when they are actually required. To demonstrate the asynchronous methodology adopted (Micropipelines), an asynchronous implementation of an 8/16-bit CISC type microprocessor (ASYNMPU), which is compatible with Intel 8086/8088 microprocessor and with several novel features, has been developed. The ASYNMPU is one of the first CISC type microprocessors using asynchronous design methodology. The design exhibits several novel features to solve the problems in building a commercially realistic asynchronous processor. For instance, a new Pre-fetch mechanism is developed to keep the instruction storage area, i.e. the asynchronous pre-fetch queue, as full as possible. The structure of the queue is constructed by using the modified Micropipelines FIFO, which is one of the first gate level implementations of the Micropipelines concept. Based on the modified Micropipelines FIFO, the data transfer and storage in the pre-fetch queue can be done with good performance as shown in the results. Since the ASYNMPU is compatible with the 8086/8088 microprocessor, its instruction set is so complicated that it comprises a wide variety of types, formats and lengths. To handle and decode these complex instructions, we have developed an extremely reliable mechanism, dubbed as Variable Instruction Length Handler (VILH). The VILH works together with the asynchronous pre-fetch queue in a way that the asynchronous pre-fetch queue provides the instruction fetching status and the VILH uses this status to calculate the length of the instruction and finds out the corresponding operation code. To execute the micro-program asynchronously, the ASYNMPU is equipped with a Controller-sequencer, which is constructed by a set of modified Micropipelines structure. The micro-instructions in ASYNMPU are RISC type instructions. They are used to translate an instruction into a sequence of small tasks. Due to the asynchronous pipelined operations, it is possible that a few requests are generated at the same time from different functional units for the access of the same register. It is known as the hazards which can jeopardize the correctness of the program execution. In fact, there are three kinds of hazards associated with an asynchronous pipelined processor. To eliminate the hazards, the solution adopted in the ASYNMPU is a register interlocking system. It is seen that although the interlocking mechanism will inevitably introduce a bubble into the system, the delay can be less than that in the synchronous systems. It is because the delay only depends on the operation time of the functional unit, which in turn depends on the input data format. It is in contrast to the delay in synchronous systems which is fixed and is relative to the time period of the operation clock. Also, the proposed Register Interlocking mechanism has a further advantage that, when the WAW hazard occurs, the operations that are not related to the contention problem in using the register can proceed first. This feature can further reduce the delay due to the bubble generated by the WAW hazard. In order to enable the ASYNMPU to be directly deployed in existing synchronous systems, a Bus Interface Unit is developed to synchronize to the operation clock to provide the interface between an asynchronous microprocessor and external synchronous systems. The main contribution here is that, although the Bus Interface Unit is synchronized by the external clock signal, the power consumption of the Bus Interface Unit in the idle state is kept to the minimum. It is due to the fully asynchronous design of the Bus Interface Unit. As the final part of our study, a new design is presented in this thesis on the asynchronous adder. By using dual-rail coding on the carry bit, the completion of an addition is accurately detected. The new asynchronous Arithmetic Logic Unit is able to deliver a mean performance similar to the synchronous ALU, while having gain on power consumption potentially. To summarize, the functionality of the ASYNMPU is independent of the outside system clock frequency. Furthermore, the power dissipation is much reduced if the processor is in the idle state. It is an inherent benefit of the asynchronous design approach. In this thesis, the design, organization, implementation and performance of the asynchronous microprocessor ASYNMPU are presented. |
| Rights: | All rights reserved |
| Access: | open access |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| b14846743.pdf | For All Users | 5.9 MB | Adobe PDF | View/Open |
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