Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor | Multi-disciplinary Studies | en_US |
| dc.contributor | Department of Electronic Engineering | en_US |
| dc.creator | Chieng, Yu-kean | - |
| dc.identifier.uri | https://theses.lib.polyu.edu.hk/handle/200/2314 | - |
| dc.language | English | en_US |
| dc.publisher | Hong Kong Polytechnic University | - |
| dc.rights | All rights reserved | en_US |
| dc.title | A chipset design for VQ encoder | en_US |
| dcterms.abstract | In this project, a VQ chip using modular arithmetic technique is designed based on the vector quantization encoding algorithm suggested by Y.H. Chan and W.C. Siu [1]. The design is simulated and implemented. This project also covered and solved the problems encountered during the use of modular arithmetic to perform the VQ algorithm. A modified searching algorithm is developed accordingly for searching the best-matched codeword for an input vector The overall performance of VQ chip is measured in terms of the computational effort, the objective performance measurement and the subjective performance measurement. Further possible improvement on the dissertation is also suggested. | en_US |
| dcterms.extent | ix, 146 leaves : ill. ; 31 cm | en_US |
| dcterms.isPartOf | PolyU Electronic Theses | en_US |
| dcterms.issued | 1999 | en_US |
| dcterms.educationalLevel | All Master | en_US |
| dcterms.educationalLevel | M.Sc. | en_US |
| dcterms.LCSH | Signal processing -- Digital techniques | en_US |
| dcterms.LCSH | Data compression (Telecommunication) | en_US |
| dcterms.LCSH | Coding theory | en_US |
| dcterms.LCSH | Algorithms | en_US |
| dcterms.LCSH | Hong Kong Polytechnic University -- Dissertations | en_US |
| dcterms.accessRights | restricted access | en_US |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| b14854132.pdf | For All Users (off-campus access for PolyU Staff & Students only) | 5.52 MB | Adobe PDF | View/Open |
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