Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor | Multi-disciplinary Studies | en_US |
| dc.contributor | Department of Electronic Engineering | en_US |
| dc.creator | Lin, Kam-lun | - |
| dc.identifier.uri | https://theses.lib.polyu.edu.hk/handle/200/2951 | - |
| dc.language | English | en_US |
| dc.publisher | Hong Kong Polytechnic University | - |
| dc.rights | All rights reserved | en_US |
| dc.title | A case study of design-for-testability of mixed signal telephony ringer integrated circuit | en_US |
| dcterms.abstract | The increased complexity of mixed analog/digital circuits and the need to control production costs is stimulating considerable research efforts worldwide to address the problem of design for testability. However, the external cables between the tester and the chip introduce parasitic that affect test quality, expensive mixed-signal testers are required to minimise circuit noise and improve on measurement techniques. In addition, it is not always possible to bring internal signals to the I/O pins without significantly degrading performance. Besides the tester accuracy issues, the time to generate and apply test patterns during production-time testing can easily become too long. An attractive alternative to cope with the problems above is to move some or all of the tester functions onto the chip itself or onto the board on which the chips are mounted. The high volume production of mixed analog/digital signal ICs is desired to reduce the cost per chip during production-time testing by the manufacturer. In this report, an efficient fault diagnostic methodology for mixed analog/digital ICs is presented. The proposed method is based on two separate test techniques: a reconfiguration-based DFT (i.e. oscillation-test strategy) and a power supply measurement technique. A CMOS telephone ringer circuit is used to demonstrate the effectiveness of the test method. The advantages of the presented test techniques include a high fault coverage, reduced test time, very simple test procedure, and elimination of the test vector process. This testing approach eliminates the need for costly specification tests and may be considered as a low-cost test method because no complicated circuit overhead is required. The results show that a multiple op-amp ring oscillation test technique can incorporate all existing op-amps on the chip and it can be achieved high fault coverage by analyzing a single oscillation frequency together with the dc current measurement. The proposed test techniques can be practically integrated in a built-in self test (BIST) structure and the oscillation frequency, which can be considered as a digital signal, can be easily interfaced to boundary scan or other test methods dedicated to the logic part of the chip under test. | en_US |
| dcterms.extent | ix, 143 leaves : ill. ; 31 cm | en_US |
| dcterms.isPartOf | PolyU Electronic Theses | en_US |
| dcterms.issued | 1999 | en_US |
| dcterms.educationalLevel | All Master | en_US |
| dcterms.educationalLevel | M.Sc. | en_US |
| dcterms.LCSH | Integrated circuits -- Testing | en_US |
| dcterms.LCSH | Hong Kong Polytechnic University -- Dissertations | en_US |
| dcterms.accessRights | restricted access | en_US |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| b14792540.pdf | For All Users (off-campus access for PolyU Staff & Students only) | 3.66 MB | Adobe PDF | View/Open |
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