|Author:||Wu, Fred Hok-choi|
|Title:||A hierarchical knockout switch for high speed information networks|
Packet switching (Data transmission)
Hong Kong Polytechnic University -- Dissertations
|Pages:||vi, 72,  leaves : ill. ; 30 cm|
|Abstract:||In 1987 October, a new, high performance packet-switching architecture, called the Knockout switch is proposed. This Knockout switch uses a fully interconnected switch fabric technology so that no switch blocking occurs where packets destined for one output interface with packets going to different outputs. Traditionally, the knockout switch is a non-blocking, higher performance switch which is suitable for broadband packet switching. It allows packet losses, but the probability of a packet loss can be kept extremely small. The main purpose for the Knockout Switch architecture has low latency, and is self-routing and non-blocking. Taking advantage of the inevitably of lost packets in a packet-switching network, the traditional design of the knockout switch uses a novel concentrator design at each output. This can reduce the number of separate buffers needed to receive simultaneously arriving packets. However, this model is very complex when the number of inputs are increased. At the same time, it introduces some additional problems both to the maintainability and fault tolerance during the modular growth. As the networks become larger and larger, the traditional knockout switch is subject to complexity and need many switch elements and buffers in order to meet the acceptable probability loss. This thesis proposes another new model - Hierarchical Knockout switch. The overall objective of the project is to enhance the knockout switch design so that it can maintain the low latency, self-routing and non-blocking feature as the traditional Knockout Switch. We will also study how to design a Hierarchical Knockout switch, which has almost the same traffic performance as the existing knockout switch but needs fewer switch elements and buffers than the existing knockout switch. The specific goals are: 1. Derive the packet loss probability for the Hierarchical Knockout Switch; 2. Optimise the design parameters so that the Hierarchical Knockout Switch can achieve minimum switching elements when the number of inputs are increasing. We have carried out a set of numerical analysis to support our conclusion. The performance will base on different design parameters (such as Input Line Number, Group Numbers and the number of output at the first stage) and will come out an analytical result on how to design the Hierarchical Knockout switch in order to achieve the optimal performance with minimum complexity. A numerical analysis program of the Knockout switch has been done to compare the loss probability for the Hierarchical model and the traditional model. The experiment result show that the complexity can be less than 90% of traditional model when the number of inputs is up to 1024 while the loss probability can still be maintained up to 10-7. Besides, the design rule for the Hierarchical model is purposed so as to simplify the multistage interconnection design. At the end of this thesis, possible future development and recommendation have been addressed.|
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