| Author: | Zheng, Xia |
| Title: | Study of short-length low-density-parity-check codes |
| Degree: | Ph.D. |
| Year: | 2009 |
| Subject: | Hong Kong Polytechnic University -- Dissertations. Signal theory (Telecommunication) Coding theory. |
| Department: | Department of Electronic and Information Engineering |
| Pages: | xi, 178 p. : ill. ; 30 cm. |
| Language: | English |
| Abstract: | Low-density parity-check (LDPC) codes can be applied to many different types of communication systems such as video broadcasting and satellite communications. However, the performance of the codes in practice may deviate a lot from the theoretical limits, achievable only by codes with infinite length. In this thesis, we will conduct a detailed investigation on the performance of short-length LDPC codes over additive white Gaussian noise (AWGN) channels. First, we look into the rich dynamical behavior occurring at the LDPC decoders when the LDPC code has a finite length. We will report the various types of bifurcation phenomena as the signal-to-noise ratio (SNR) increases. By linearizing the iterative equations used for decoding the signals, we are able to evaluate the eigenvalues corresponding to the fixed points. Based on the eigenvalues, we can further characterize the properties of the fixed points. In addition, we make use of a simple feedback technique in an attempt to improving the convergence rate of the decoder at the waterfall (medium-SNR) region. Then, we attempt to "optimize" the distributions of the variable-node degrees and check-node degrees such that lower error rates can be produced. Although some "optimized" variable-node and check-node degree distributions have already been reported in the literature, they are found based on the assumption that the LDPC codes having an infinite length. Therefore, the error performance of a finite-length LDPC code obeying such degree distributions may not be "optimized" and there are possibilities that codes following other degree distributions may produce better performance in terms of block/bit error rates (BLERs/BERs). Since the LDPC decoders rely on passing messages iteratively between the set of variable nodes and the set of check nodes, decreasing the short average path length (APL) will no doubt accelerate the exchange of messages among the variable nodes, thereby reducing the number of iterations the decoder algorithm takes to converge. Inspired by the short average path length (APL) between nodes in complex networks with scale-free (SF) degree distributions, we make the first attempt in applying complex-network theories to communications engineering and build short-length LDPC codes with variable-node degrees following SF degree distributions. Not only have we evaluated the theoretical performance of our SF-LDPC codes, but also the simulated error rates. Furthermore, we compare our results with those of other well-known LDPC codes. As we simulate the BLER of short-length LDPC codes with an increasing SNR, we further observe that the BLER is decreasing with a much lower rate when the SNR becomes large, implying that the BLER has reached an error floor. Investigations have revealed that the block errors at the high SNR region are mainly caused by trapping sets (TSs) with their induced connected subgraphs forming one or more cycles. To easily differentiate trapping sets with (i) no cycle, (ii) a single-cycle or (iii) multiple cycles, we introduce a new parameter, namely cycle indicator. Moreover, we define a "primary trapping set (PTS)" with an aim to identifying harmful TSs to the decoder. Realizing the types of PTSs that are more likely to contribute to the error floor, we propose a code-construction method that aims to avoid such harmful PTSs. Codes so constructed will be evaluated and compared with those built using other mechanisms. Finally, as we keep increasing the SNR, a point will be reached where running Monte Carlo (MC) simulations will no longer be feasible. It is because the BLER has become so low that it will take an extremely long simulation time before an adequate number of errors are collected. In order to evaluate more effectively and efficiently the extremely low error rates of the codes at the high SNR region, we propose a simulation scheme that combines the use of importance sampling (IS) and PTS identification. Compared with the MC simulations, the proposed IS scheme produces speed-up gains of up to 3.9184 x 109. |
| Rights: | All rights reserved |
| Access: | open access |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| b2306724x.pdf | For All Users | 4.39 MB | Adobe PDF | View/Open |
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