Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor | Department of Electronic and Information Engineering | en_US |
| dc.creator | Zhao, Yue | - |
| dc.identifier.uri | https://theses.lib.polyu.edu.hk/handle/200/6761 | - |
| dc.language | English | en_US |
| dc.publisher | Hong Kong Polytechnic University | - |
| dc.rights | All rights reserved | en_US |
| dc.title | Implementation of decoders for LDPC block codes and LDPC convolutional codes based on the parallel architecture of the GPUS | en_US |
| dcterms.abstract | With the use of belief propagation (BP) decoding algorithm, low-density parity-check (LDPC) codes can achieve near-Shannon limit performance. LDPC codes can accomplish bit error rates (BERs) as low as 10⁻¹⁵ even at a small bit-energy-to-noise-power-spectral-density ratio (Eb/N0). In order to evaluate the error performance of LDPC codes, simulators running on central processing units (CPUs) are commonly used. However, the time taken to evaluate LDPC codes with very good error performance is excessive. For example, assuming 30 iterations are used in the decoder, our simulation results have shown that it takes a modern CPU more than 7 days to arrive at a BER of 10⁻⁶ for a code with length 18360. Implementing the decoder using field programmable gate array (FPGA) is one solution but the cost is high and the development period is very long. Moreover, the FPGA codes are not flexible. In this thesis, efficient LDPC block-code decoders/simulators which run on graphics processing units (GPUs) are proposed. Both standard BP decoding algorithm and layered decoding algorithm are used. By optimizing the data structures of the messages used in the decoding process, both the read and write processes can be performed in a highly parallel manner by the GPUs. In addition, a thread hierarchy avoiding the divergence of the threads is deployed, and it can maximize the efficiency of the parallel execution. With the use of a large number of cores in the GPU to perform the simple computations simultaneously, our GPU-based LDPC decoder can obtain hundreds of times speed-up compared with a CPU-based simulator. We also implement the decoder for the LDPC convolutional codes (LDPCCC). The LDPCCC is derived from a pre-designed quasi-cyclic LDPC block code with good error performance. Compared to the decoder based on the randomly constructed LDPCCC code, the complexity of the proposed LDPCCC decoder is reduced due to the periodicity of the derived LDPCCC and the properties of the quasi-cyclic structure. Moreover, by decoding multiple code frames together, the decoder can always access the global memory in a coalesced manner. The GPU-based LDPCCC decoder displays an excellent error performance and it can achieve up to 200 times speed-up compared with the CPU-based simulator. | en_US |
| dcterms.extent | xix, 91 p. : ill. ; 30 cm. | en_US |
| dcterms.isPartOf | PolyU Electronic Theses | en_US |
| dcterms.issued | 2012 | en_US |
| dcterms.educationalLevel | All Master | en_US |
| dcterms.educationalLevel | M.Phil. | en_US |
| dcterms.LCSH | Decoders (Electronics) | en_US |
| dcterms.LCSH | Error-correcting codes (Information theory) | en_US |
| dcterms.LCSH | Graphics processing units. | en_US |
| dcterms.LCSH | Hong Kong Polytechnic University -- Dissertations | en_US |
| dcterms.accessRights | restricted access | en_US |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| b25302231.pdf | For All Users (off-campus access for PolyU Staff & Students only) | 1.93 MB | Adobe PDF | View/Open |
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