| Author: | Lo, Wing-Yee |
| Title: | Study of multi-standard video codec processor architecture : a quantitative approach |
| Degree: | Eng.D. |
| Year: | 2012 |
| Subject: | High performance processors. Signal processing -- Digital techniques. Hong Kong Polytechnic University -- Dissertations |
| Department: | Faculty of Engineering |
| Pages: | xii, 107 leaves : ill. (some col.) ; 30 cm. |
| Language: | English |
| Abstract: | The emergence of advanced video coding standards such as H.264/AVC has led to a tremendous demand of high performance video processors. Not only due to the substantially increased complexity, these advanced video coding standards are often required to be used in real-time applications that makes their implementation become particularly computation-demanding. Current research on high performance video processors focuses on exploring parallelism in the video processing algorithms of these standards and mapping it to the architectural design of parallel processors. In order to achieve high performance, it is generally known that a video processor should extensively make use of all levels of parallelism in the execution, which include the data level parallelism (DLP), instruction level parallelism (ILP) and thread level parallelism (TLP). To exploit the DLP in the execution, Single-Instruction-Multiple-Data (SIMD) is a popular approach in traditional parallel processors. In this thesis, we firstly detail the analysis of the performance bottlenecks of SIMD when executing video processing algorithms. Based on the analysis result, two novel features are proposed for the design of SIMD video processor architecture: (i) parallel memory structure with variable block size and word length support, and (ii) configurable SIMD. The new parallel memory structure allows data access of different block sizes and different word lengths efficiently. The configurable SIMD structure allows almost "random" register file access and slightly different operations in the arithmetic and logic units (ALUs) inside SIMD. When comparing with the conventional designs, the proposed SIMD architecture can have a further speedup of 2.1X to 4.6X when implementing H.264/AVC kernel functions. As the second part of this study, an almost-cycle-accurate performance model for video processor architecture design exploration is proposed. The performance model allows efficient and comprehensive evaluation of video processor architectures that facilitates design enhancement. It is a trace and execution driven model with analytical feedback. The simulation time is short but the result is accurate. In this study, we started from a baseline video processor architecture which was based on two analyses: (i) the SIMD bottleneck analysis in the first part of the study and (ii) the parallel processing architecture overhead study. In addition, the baseline architecture was designed with the goal of maximizing all levels of parallelism in execution. It integrates a SIMD architecture (DLP) with superscalar support (ILP) and multithreading capability (TLP). By using the proposed performance model and the design exploration process, we investigated the features of that video processor where further architectural enhancement can be made for implementing the advanced video coding standards such as H.264/AVC, AVS-M and MPEG4. Simulation result shows that, when encoding digital videos in CIF resolution at 25fps real-time based on the abovementioned three video coding standards, the optimized video processor is only required to run at a clock rate of 70, 80 and 40MHz respectively. It outperforms other video processors in both cost and performance perspectives. |
| Rights: | All rights reserved |
| Access: | restricted access |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| b25202273.pdf | For All Users (off-campus access for PolyU Staff & Students only) | 4.13 MB | Adobe PDF | View/Open |
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