|Title:||Analysis and development of short-distance wired communications|
Hong Kong Polytechnic University -- Dissertations
|Department:||Faculty of Engineering|
|Pages:||xii, 102 p. : ill. ; 30 cm.|
|Abstract:||Wired communications is one of the major forms of electronic communications. There are two types of communication interfaces in computer systems: internal interfaces and external interfaces. Examples of internal interfaces are Serial Advanced Technology Attachment (SATA), Personal Computer Interface (PCI), PCI Express (PCIe), etc., whereas examples of external interfaces are Universal Serial Bus (USB), Thunderbolt, External SATA (eSATA), etc. SATA is an important standard of PC communication with a transfer rate of 6.0 Gbit/s. It is a computer bus interface which connects host bus adapters to mass storage devices such as optical drives, hard disk drives, etc. Thunderbolt is a new transmission technology jointly developed by Intel and Apple. It allows for the connection of external peripherals to a computer with the transfer speed of 10 Gbit/s. USB 3.1 is the latest USB standard with a data rate of 10 Gbit/s, whereas USB 3.0, which is the mainstream USB standard for computers and various peripheral and storage devices, offers a rapid transmit rate of 5 Gbit/s. A closer look at the speci.cation of USB 3.0 shows that the clock and data recovery (CDR) is an essential module of the physical layer of USB 3.0. CDR is used to extract the clock signal from the bit-stream. On the receiver side, a clock signal is generated from a frequency generator. This reference clock is adjusted to align with the changes of the bit-stream. Since transmitting digital information over a long distance is necessary, the encoded bit-stream and clock signal are embedded and serialised to minimise the number of signal wires. The data signal and clock signal are transmitted together and, hence, are subject to the same delay. A coding is used to achieve bounded disparity and DC-balance. Furthermore, the coding must provide an adequate number of toggled states to allow the clock signal to be recovered from the data. A common line code is 8b/10b, which can fulfill the mentioned conditions and translate the symbols from 10-b to 8-b for decoding and the symbols from 8-b to 10-b for encoding. Since the CDR circuit plays a crucial role in every high-speed serial communication system, a novel architecture has been proposed for the CDR circuit. In the proposed CDR architecture, it is modified from the architecture stated in . However, 8 D-Flip Flop based slices with eight-phase clocks are used for the phase detector instead of the bang-bang phase detector. A voter circuit is used as the decimator circuit for fast calculation. In addition, a digital-to-phase converter (DPC) is used to select the corrected eight-phase clocks instead of using a voltage controlled oscillator (VCO) to generate the phase clocks. The proposed implementation of the CDR circuit does not depend on the specific analog process and it can provide higher immunity to noise. Compared with the traditional CDR circuit, the resulting signal of the proposed CDR circuit is less affected by noise and the transfer function of the transmission medium. In addition, the size of the CDR circuit is small when compared with other implementations using 0.11 μm or more advanced technology. Thus, the manufacturing cost of the proposed design is significantly lower than the others.|
Applications of the high-speed serial bus can be found in contemporary computer systems, in which the internal hard disk is a crucial device. The main function of a hard disk is to store software and data. Hence, a disk that fails or is unstable substantially affects the operation and performance of the computer system. However, the communication channel of the hard disk is a noisy channel. Because data errors can occur during reading or writing, codecs must be implemented to increase the accuracy of accessing data from the storage device during high-speed communication. The most common method for conducting this process is to use the redundant array of independent disk (RAID) system with coding for error detection and correction. The RAID system combines several hard disks to function as a single hardware for redundancy checking and double storage. A novel, quasi-cyclic low-density parity check (QC-LDPC) coding  is used for the RAID system with the function of error correction and detection. The proposed coding is a layered QC-LDPC with excellent error performance, low complexity, high throughput and high code rate. A chip is designed to illustrate the function of the QC-LDPC codec. In the chip design, a QC-LDPC decoder and a QC-LDPC encoder are included in the RAID system. The QC-LDPC decoding circuit consists of a few thousands of check nodes and variable nodes. Each node contains a 64x4 b random access memory (RAM) including 1440 RAMs inside the circuit. The chip is designed to match the data rate of USB 3.0, which is used as an external interface for the RAID system.
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