Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor | Faculty of Engineering | en_US |
| dc.contributor.advisor | Sham, Chiu-wing (EIE) | - |
| dc.creator | Lu, Qing | - |
| dc.identifier.uri | https://theses.lib.polyu.edu.hk/handle/200/8007 | - |
| dc.language | English | en_US |
| dc.publisher | Hong Kong Polytechnic University | - |
| dc.rights | All rights reserved | en_US |
| dc.title | Architecture design of QC-LDPC decoder with cyclicly-coupled codes | en_US |
| dcterms.abstract | Out of the need for a superb forward error correction (FEC) scheme, the well known low-density parity-check (LDPC) codes arouse our interest. With Belief Propagation (BP) decoding, this class of channel codes demonstrates a limit-approaching ability but implementation issues remain. This thesis focus-es on designing a decoder architecture with excellent error performance, high throughput and low complexity. In this work, a sub-class of LDPC codesquasi-cyclic LDPC (QC-LDPC) codesis investigated and decoded with quantized sum-product algorithm (SPA). An optimized RAM-based decoder architecture with extraordinary performance is proposed. Considering the implementation issues, codes with cyclicly coupled structure are proposed. At the cost of a slight increase in architectural redundancy, the decoders for these codes achieve a significant improvement in bit error rate (BER). The proposed architecture has been implemented onto a field programmable gate array (FPGA) for a 98304-bit 5/6-rate cyclicly-coupled QC-LDPC (CC-QC-LDPC) code. The experimental results show no error floor above a BER of 10¹⁴. As the bit-energy-to-noise power-spectral-density ratio (Eb/N0) goes up to 3.50 dB, no errors are detected among the 1.14 × 10¹⁶ decoded bits. Besides, the architectural throughput of our implementation is up to 1.9 Gbps at a clock rate of 100 MHz. | en_US |
| dcterms.extent | xi, 78 leaves : illustrations ; 30 cm | en_US |
| dcterms.isPartOf | PolyU Electronic Theses | en_US |
| dcterms.issued | 2014 | en_US |
| dcterms.educationalLevel | All Master | en_US |
| dcterms.educationalLevel | M.Sc. | en_US |
| dcterms.LCSH | Signal processing. | en_US |
| dcterms.LCSH | Error-correcting codes (Information theory) | en_US |
| dcterms.LCSH | Hong Kong Polytechnic University -- Dissertations | en_US |
| dcterms.accessRights | restricted access | en_US |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| b28110602.pdf | For All Users (off-campus access for PolyU Staff & Students only) | 4.45 MB | Adobe PDF | View/Open |
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