Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor | Department of Electronic and Information Engineering | en_US |
| dc.contributor.advisor | Ho, Ivan (EIE) | - |
| dc.contributor.advisor | Schafer, B. Carrion (EIE) | - |
| dc.creator | Chen, Jieshi | - |
| dc.identifier.uri | https://theses.lib.polyu.edu.hk/handle/200/8043 | - |
| dc.language | English | en_US |
| dc.publisher | Hong Kong Polytechnic University | - |
| dc.rights | All rights reserved | en_US |
| dc.title | FPGA based feature detection and networking system | en_US |
| dcterms.abstract | In today's traffic monitoring system, image processing with software cannot meet the requirement of real-time processing demand because of its serial data processing structure. In this thesis, one hardware based image processing and networking system prototype is raised out to achieve the high throughput real-time image processing as well as data transmission. The hardware architecture is mainly composed of four parts: raw data collecting part, image processing part, data transmission part and control part. The result of the design is to detect the number plate in a real-time system, locate the position of the number-plate and transport the data from FPGA side to PC through Ethernet networking system. There are three highlights and contributions for this design: 1. It introduces a new way for designing the hardware architecture by using ANSI-C instead of RTL so that to ease and shorten the design period. For number-plate detection part, all the algorithm is finished in pure ANSI-C and then using a tool called CyberWorkBench to verify the correctness of the design and automatically generate the Verilog code for implementation. 2. In the past designs, the designer usually focuses on either image processing or data transmission. This design fully provides a prototype for integrating both these two parts in one on board system, which is also a key difficult point for the design. 3. The design can tolerate high data throughput at the rate of 60 frames per second, both for image processing side and networking data transmission side. Thus, this design is suitable and ideal for processing real-time data. Overall, the design provides a complex hardware based all-in-one system that can collect raw data, do image processing and transmit data through network. The implementation tools for this design is CyberWorkBench, Quartus II and Wireshark. | en_US |
| dcterms.extent | 88 pages : illustrations | en_US |
| dcterms.isPartOf | PolyU Electronic Theses | en_US |
| dcterms.issued | 2015 | en_US |
| dcterms.educationalLevel | All Master | en_US |
| dcterms.educationalLevel | M.Sc. | en_US |
| dcterms.LCSH | Data transmission systems. | en_US |
| dcterms.LCSH | Computer networks. | en_US |
| dcterms.LCSH | Digital communications. | en_US |
| dcterms.LCSH | Hong Kong Polytechnic University -- Dissertations | en_US |
| dcterms.accessRights | restricted access | en_US |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| b28171068.pdf | For All Users (off-campus access for PolyU Staff & Students only) | 3.96 MB | Adobe PDF | View/Open |
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