|Title:||In situ programmable SoC design space exploration|
|Advisors:||Carrion Schafer, Benjamin (EIE)|
|Subject:||Hong Kong Polytechnic University -- Dissertations|
Systems on a chip -- Design and construction
|Department:||Department of Electronic and Information Engineering|
|Pages:||xiii 57 pages : color illustrations|
|Abstract:||Until recently, Chips' performance improvement was mainly achieved through transistor scaling and increased clock frequency. As increased power consumption now dominates this is getting more diffcult. Thus, to achieve higher performance within a given power budget, most circuits are now heterogeneous Multiprocessor Systems-on-Chips (MPSoCs), which typically include embedded microprocessors, memory controllers, memories and dedi-cated hardware accelerators (HWAccs), all interconnected through a single bus, bus-hierarchies or even networks-on-chip (NoCs). Even FPGA vendors have introduced Confgurable SoCs (CSoC), e.g. Altera's Cyclone SoC and Xilinx's Zynq family. Companies have started to rely on High-Level Synthesis (HLS) to increase their design productivity and making use of third party behavioral IPs (3PBIPs) to meet their tight schedules. C-Based design has many advantages compared to traditional RTL design. The most salient ones include, the increase in design productivity, which allows design teams to meet the increasingly stringent time-to-market requirements, the ability to create smaller designs compared to hand-coded RTL due to its ability to maximize resource sharing and the possibility of generating a set of different micro-architectures with different area vs. performance trade-offs without having to modify the original behavioural description, also called Design Space Exploration (DSE). The main work in this thesis is the in situ characterization of CSoC in which behavioral IPs (BIPs) are mapped as loosely coupled hardware accelerators (HWaccs) onto the reconfgurable fabric. As the thesis will show, experimental results on a Terasic DE1-SoC board containing a Cyclone V SoC FPGA with dual core ARM A-9 processors, indicate the effectiveness of our proposed flow. One problem faced during the work done at this thesis was that there were no benchmarks that can be directly mapped onto these CSoC to conduct research in HW/SW co-design as well as to teach HW/SW co-design. Thus an open source HW/SW co-design benchmark suite based on the Synthesizable benchmark suite (S2CBench)  was also created and made public to the community at . These designs include the FPGA confguration file (SOF) and a pre-compiled SW program (EXE), which allow to immediately have a HW/SW co-dossing system up and running.|
|Rights:||All rights reserved|
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