Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor | Department of Electronic and Information Engineering | en_US |
| dc.creator | Hui, Wai-lam | - |
| dc.identifier.uri | https://theses.lib.polyu.edu.hk/handle/200/1007 | - |
| dc.language | English | en_US |
| dc.publisher | Hong Kong Polytechnic University | - |
| dc.rights | All rights reserved | en_US |
| dc.title | Algorithms and processor structures for motion picture compression | en_US |
| dcterms.abstract | Recent progress in video compression algorithms and VLSI technology has made it possible to store and transmit digital video in many applications. Related standard activities in video compression are also moving rapidly. Two central components of these emerging standards are the motion estimation and the Discrete Cosine Transform (DCT), which intend to remove the spatial and temporal redundancies in video sources. And it is known that the computational requirements are the most critical for real-time applications. It is necessary to develop custom hardware and efficient algorithms to enable real-time applications while to reduce the manufacturing cost of the Video Codec. It is well known that the DCT approaches the statistically optimal KLT for highly correlated signals. Fast algorithms for its implementation are developed to reduce the computational complexity. With the growing applications of the DCT, it is desirable to develop a modular and reusable DCT processor to reduce system cost. For this purpose, a low hardware complexity Discrete Cosine Transform Processor, with high speed operation and regular structure, is designed and implemented. The DCT processor features bit-serial approach and parallel operation with multiple operation elements. With the use of signed digit representation of the DCT coefficients technique, more than 75 percent reduction on the hardware for the DCT kernel matrix multiplication can be saved. The optimized kernel matrix multiplier exhibits highly pipeline operations and the maximum achievable operation frequency of the processor is 45MHz. The implementation of the DCT processor including external interface circuits uses about 4500 gates. The widely used block motion estimation and compensation algorithms are considered to he the most efficient and yet a simple technique for the reduction of temporal redundancies. In this thesis, a new pixel decimation technique based on a set of the pixel patterns for block motion vector estimation is proposed to compensate the drawback in the approach using pixel decimation. For regular pixel decimation, regular patterns are used for computing the matching criterion to estimate the motion vector. The results can easily be misled by some image textures. Thus, we define some "most representative pixel patterns" and make the selection according to the content in each image block for the matching criterion. Our approach can efficiently compensate the drawback in uniform pixel decimation. Computer simulations show that this technique is close to the performance of the full search, and has a significant reduction on computational complexity as compared with other pixel decimation algorithms in the literatures. Also, it is more convenient for hardware realization as compared with the fully adaptive pixel decimation. Adaptive algorithm has many advantages over fixed strategy algorithms. However, the variation on the execution time for different video scene is difficult for its realization. A multiprocessor system is designed for the realization of the newly proposed Edge Oriented Adaptive Motion Algorithm. With the technique of task decomposition and a predetermined execution profile, a simple scheduling strategy is derived and the idling time of each processor is reduced dramatically. For the realization using ASIC design, a speedup of 3.5 is achievable by making use of four Processing Elements with an overhead of less than 15% hardware complexity. One of the problems of the block motion estimation is that blocks located on boundaries of moving objects are not estimated accurately. It is considered to be the most objectionable distortion by human observer. In this thesis, a new edge-masked matching criterion for block motion estimation and its hardware architecture are also presented. The proposed matching criterion makes use of edge features to modify the conventional matching criterion for computing the motion information. Experimental results and a custom hardware design show that the new matching criterion has removed the most visually disturbing artifacts with a slight increase in hardware complexity, and the motion-compensated prediction frames are virtually error-free. | en_US |
| dcterms.extent | x, 109 leaves : ill. (some col.) ; 31 cm | en_US |
| dcterms.isPartOf | PolyU Electronic Theses | en_US |
| dcterms.issued | 1999 | en_US |
| dcterms.educationalLevel | All Master | en_US |
| dcterms.educationalLevel | M.Phil. | en_US |
| dcterms.LCSH | Video compression | en_US |
| dcterms.LCSH | Algorithms | en_US |
| dcterms.LCSH | Digital video | en_US |
| dcterms.LCSH | Coding theory | en_US |
| dcterms.LCSH | Hong Kong Polytechnic University -- Dissertations | en_US |
| dcterms.accessRights | open access | en_US |
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| File | Description | Size | Format | |
|---|---|---|---|---|
| b14732610.pdf | For All Users | 4.17 MB | Adobe PDF | View/Open |
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