| Author: | Liu, Shuangnan |
| Title: | Design and optimization of behavioral dataflows |
| Advisors: | Carrion Schafer, Benjamin (EIE) Lau, C. M. Francis (EIE) |
| Degree: | Ph.D. |
| Year: | 2019 |
| Subject: | Hong Kong Polytechnic University -- Dissertations Data flow computing Electronic data processing |
| Department: | Department of Electronic and Information Engineering |
| Pages: | xvi, 134 pages : color illustrations |
| Language: | English |
| Abstract: | Dataflow computing is a computational paradigm that uses the flow of data streams to accelerate the computation of tasks. Thus, it is also known as stream computing. It is essential in multiple domains, such as image processing and digital signal processing, where data processing throughput is critical. Modern heterogeneous System on Chips (SoCs) exploit this computational paradigm to accelerate the computation of specific computationally intensive functions mapped as hardware accelerators on the SoC. Moreover, designing these accelerators in low-level hardware description languages is tedious, error-prone and takes a relatively long time. Thus, companies have started using High Level Synthesis (HLS). This thesis investigates the use of HLS to design and optimize dataflow hardware systems and uses Field Programmable Gate Arrays (FPGAs) as a test bed to demonstrate the usability of the developed methods. In particular, this thesis first investigates the effects of pin multiplexing on individual hardware accelerators given as untimed behavioral descriptions that we call Behavioral IPs (BIPs), written in C or SystemC and addresses the issues of port assignments and mappings. Next, it explores the design space of dataflow systems considering the inter-module connections to identify a set of Pareto optimal configurations as multiple conflicting objectives need to be optimized such as area and latency. Design teams now typically also prototype and emulate Application Specifc Integrated Circuit (ASIC) designs on FPGAs. Thus, we study how to automatically convert optimized dataflows for an ASIC technology to FPGAs based on machine learning techniques. The proposed method can avoid having to fully re-explore the design when an FPGA is targeted and achieves a speedup from hours to seconds while preserving the accuracy. This technique is extended to map complete dataflow systems from ASIC to FPGA platforms given full consideration of the design space of individual modules and the inter-module connections. Finally, the thesis describes a strategy to map dataflows onto runtime reconfigurable FPGAs given specific area and performance constraints. |
| Rights: | All rights reserved |
| Access: | open access |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 991022287148703411.pdf | For All Users | 1.36 MB | Adobe PDF | View/Open |
Copyright Undertaking
As a bona fide Library user, I declare that:
- I will abide by the rules and legal ordinances governing copyright regarding the use of the Database.
- I will use the Database for the purpose of my research or private study only and not for circulation or further reproduction or any other purpose.
- I agree to indemnify and hold the University harmless from and against any loss, damage, cost, liability or expenses arising from copyright infringement or unauthorized usage.
By downloading any item(s) listed above, you acknowledge that you have read and understood the copyright undertaking as stated above, and agree to be bound by all of its terms.
Please use this identifier to cite or link to this item:
https://theses.lib.polyu.edu.hk/handle/200/10177