| Author: | Balachandran, Anjana |
| Title: | On the robustness of behavioural circuit design : from fault-tolerance to hardware security |
| Advisors: | Carrion Schafer, Benjamin (EIE) Lau, C. M. Francis (EIE) |
| Degree: | Ph.D. |
| Year: | 2021 |
| Subject: | Systems on a chip Fault tolerance (Engineering) Hong Kong Polytechnic University -- Dissertations |
| Department: | Department of Electronic and Information Engineering |
| Pages: | xix, 109 pages : color illustrations |
| Language: | English |
| Abstract: | The continuous demand for electronic products is pushing the semiconductor industry to deliver new and more advanced products at shorter time frames. These rapid developments have partially been made possible with the continuous shrinking of transistors, also known as Moore's law. One of the problems with smaller transistors is that they are also more susceptible to transient errors. These errors can affect the correct operation of electronic equipment, and hence, their reliability. Especially, transient errors could turn out to be fatal in safety-critical applications. Thus, it is natural to expect a higher level of reliability in such safety-critical systems. Reliability here refers to the systems' ability to be available during adverse conditions. Factors that prevent these systems from being available can be unintentional or intentional. Unintentional factors that induce a fault include atmospheric radiations, harsh environmental conditions or energized particles. Intentional factors are mainly due to the fact that many Integrated Circuit (IC) design companies these days are fabless and they rely on offshore foundries to manufacture their chips. These ICs could be maliciously altered by rogue elements within the design and manufacturing chain, preventing such systems from functioning correctly. Moreover, complex System-on-chips (SoCs) now include a wealth of information that attackers try to extract to profit economically. This ranges from stealing the Intellectual Property (IP) of the designs to secret encryption keys stored in the SoCs. Thus, it is important that IC design seamlessly integrates fault tolerance techniques to mitigate faults induced due to unintentional factors with hardware security as a new design parameter. The main fault tolerance approaches have relied on building N-Modular Redundant system (NMR) mainly at the Register Transfer Level (RTL). With the increase in logic density, modern ICs are now complex System-on-Chips (SoCs). Thus, new design methodologies have been developed to move up the level of Very Large Scale Integration (VLSI) design abstraction from the RTL to the behavioural level. Thus, it is crucial to revisit the problem of fault-tolerant VLSI design for SoCs designed using higher-levels of abstractions. Moreover, hardware security primarily relies on logic locking techniques including key gate insertions at the RT-level or gate level. Modern High-Level Synthesis (HLS) tools allow to more effectively lock behavioural IPs and make them more robust against several types of attacks. Thus, revisiting hardware security using HLS could open new paths towards designing secure ICs. This thesis deals with these important issues and proposes techniques to make behavioural SoCs more robust against soft errors and protect these SoCs from malicious alterations or IP theft through functional locking. The main goal is to address these important issues by raising the level of VLSI design abstraction from the RT-level to the behavioural level. |
| Rights: | All rights reserved |
| Access: | open access |
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