Author: | Wang, Cong |
Title: | P-type semiconductor Tellurium growth and high-performance P-type field effect transistor fabrication |
Advisors: | Chai, Yang (AP) |
Degree: | Ph.D. |
Year: | 2024 |
Subject: | Field-effect transistors Semiconductors Two-dimensional materials Hong Kong Polytechnic University -- Dissertations |
Department: | Department of Applied Physics |
Pages: | xxiii, 101 pages : color illustrations |
Language: | English |
Abstract: | Complementary n- and p-type field effect transistors (FET) are the foundation of modern semiconductor electronics. Researchers have synthesized many kinds of n-type semiconductors to fabricate high performance n-type FETs. An elemental p-type two-dimensional (2D) material (e.g., tellurene (Te)) has uncommon crystal structures and properties. Nevertheless, there are still many great challenges to grow high crystalline and large size Te by using conventional vapor deposition method. Firstly, we design a Copper foil assisted alloy-buffer-controlled method to achieve the aligned, single crystalline Te with thickness thin to < 10 nm on mica substrate. The most significant role in this method is to form the Copper-Tellurene (Cu-Te) alloy. This alloy formation achieves the precursor distribution uniform both spatially and temporally which cannot be controlled in conventional vapor growth process. From transmission electron microscopy (TEM) characterization and theoretical calculations, we find that Te grows in the [110] direction along the [600] direction of mica substrate. This alignment growth is due to the lattice mismatch of Te and mica substrate is small to 0.15 % and their strong binding energy. The as-grown Te flakes shows smooth surface and high uniformity. This method successfully achieves the controlled growth of 2D Te. Next in this thesis, we demonstrate a strategy to fabricate high performance p-type FETs. As the device size decreases down to nanoscale, the contact resistance becomes a dominant factor of device performance. Researchers have shown ultralow contact resistance for n-type two-dimensional (2D) semiconductors with indium, bismuth, and antimony. However, the low-resistance electrical contact to p-type 2D semiconductors proves to be very challenging, which makes it difficult to construct complementary devices. Here we introduce an ultrathin (1.2 nm) Selenium (Se) interfacial layer at the contact region. Se has the highest work function in the periodic table of elements, which greatly reduces the Schottky barrier height (SBH) with p-type semiconductors. The semiconducting characteristics of Se can also mitigate the gap states induced by common metal electrodes. With the Se interfacial layer of p-type WSe2 transistors, the saturated current density increases from 17.78 μA μm-1 to 124.62 μA μm-1; and the contact resistance decreases from 10.2 kΩ·μm to 2.2 kΩ·μm. Lastly, we extended our Se interfacial layer contact methodology to other p-type semiconductors (black phosphorus (BP), semiconducting carbon tubes (CNT)), providing a reliable method to establish low-resistance electrical contact to nanoscale p-type semiconductors. The Se interfacial layer contact can also be applied to dry transfer method to fabricate p-type FETs, that has comparable device performances compared to transistors fabricated by Se interfacial layer deposition. Our results provide a great opportunity to fabricate p-type FETs array with easy implemented way. In conclusion, we demonstrate a vapor deposition method by using a Cu-Te intermediate to successfully grow aligned Te with high crystalline. This method provides great potential for growing high quality and single crystalline Te flakes. We present a reliable method to reduce the contact resistance of p-type 2D transistors using standard laboratory technology. By adopting the ultrathin Se interfacial layer with semiconducting characteristics and the highest work function, we successfully suppress the metal-induced gap states and substantially reduce the Schottky barrier height. |
Rights: | All rights reserved |
Access: | open access |
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