|Title:||A low power high performance 64KBit CMOS SRAM design|
|Subject:||Hong Kong Polytechnic University -- Dissertations|
Metal oxide semiconductors, Complementary
Random access memory
|Department:||Department of Electronic and Information Engineering|
|Pages:||108 leaves : ill. ; 30 cm|
|Abstract:||A 64KBit CMOS SRAM with an access time of 55ns under single 5V supply has been developed with 0.35um process technology to provide fast access and low power dissipation by using highly optimized architecture. Hierarchical simplified models are developed to determine the delay, power and area of the SRAM. To achieve the requirement of the design, new SRAM cell with area of 15.81um2, new hierarchical decoding scheme, new read & write control scheme, differential voltage sense amplifier and data input & output buffer were developed. This work evaluates the voltage and delay limitation of CMOS technology and how SRAM circuits can maximize the utility of CMOS device without degraded reliability and performance. Process enhancement is not necessary to implement the circuits. The contribution of this work include,  evaluation of the CMOS device reliability issues related to the SRAM circuits,  development of a dual voltage SRAM to achieve the low power and small area of the SRAM design,  development of a reduced element word line driver for hierarchical X decoder. With these design techniques building blocks necessary for SRAM circuits can be implemented. This can reduce the 64KBit SRAM access time to 70% and power dissipation to 50% of the conventional high speed CMOS SRAM.|
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