Author: Tang, Siu-hei
Title: On the issues of power dissipation reduction in CMOS combinational logic circuits
Degree: M.Sc.
Year: 2000
Subject: Logic circuits
Hong Kong Polytechnic University -- Dissertations
Department: Multi-disciplinary Studies
Department of Electronic and Information Engineering
Pages: ix, 118 leaves : ill. ; 31 cm
Language: English
Abstract: Due to increased circuit speed and density, power consumption in CMOS VLSI chips becomes increasingly important. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications. A new model for estimating dynamic power dissipation in CMOS combinational circuits at differing voltages is proposed by Sri Parameswaran and Hui Guo [1] to facilitate VLSI designers to build systems with high performance and lower power consumption. The Proposed model deals with power dissipation of CMOS combinational circuits running at saturation frequencies, where the output voltage does not reach 100% of the supply voltage and the output voltage is almost a triangular waveform. This model shows that the dynamic power consumption at saturation frequencies is only dependent on the supply voltage and is independent of load capacitance and switching speed. Moreover, it also shows that when a circuit is working in the saturation frequency range, as the frequency is increased, the performance/power ratio is increased. With this power estimation model, it can be used to design systems that contain different combinational logic blocks to have different supply voltages. The power dissipation of such systems would be lower when compare to the same systems with a single supply voltage. The purpose of this dissertation is to study and verify the theory proposed in this power estimation model used for CMOS combinational circuits. In addition, selected CMOS combinational circuits will be simulated using SPICE to verify the concept of power dissipation reduction using this model.
Rights: All rights reserved
Access: restricted access

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