|Author:||Gorla, Naga Sujatha|
|Title:||Mixed-signal built-in self-test|
|Subject:||Mixed signal circuits|
Hong Kong Polytechnic University -- Dissertations
|Department:||Department of Electronic and Information Engineering|
|Pages:||xi, 92 leaves : ill. ; 30 cm|
|Abstract:||Due to the rapid advances in systems integration especially in the fields of multimedia, mobile communications and portable data systems, the growing need for mixed-signal integrated circuits (ICs) has accelerated efforts in the design and testing of analog circuits. Integrating both digital and analogue circuits on a single chip improves performance and reduces board size and cost. As a result, the circuits become more complex and hence raise the problem of design for testability. A traditional approach to testing a mixed signal IC is to partition the circuit into several sub-blocks, such that the inputs and the outputs from each sub-block can be directly controlled and observed. However the partition of a mixed-signal IC is a difficult proposition, since testability analysis is computationally very expensive and circuit partitioning requires the design and integration of test specific hardware. Recently, a defect oriented technique known as Oscillation-based Test Methodology (OTM) has been widely studied as a core for a built-in self-test structure, to improve the design testability. The methodology is based on converting the whole circuit under test into an oscillator wherein the oscillation frequency is compared to the nominal oscillation frequency. Any deviation in the observed oscillation frequency or no oscillation indicates possible fault in the circuit under test. The OTM offers some unique advantages, such as the testing of a circuit without external stimuli and a reduction in test time due to the limited number of oscillation frequencies. Therefore, OTM can be easily implemented. However, one of the main disadvantages is that, it cannot precisely identify the fault location. Hence, in this research work, an attempt is made to improve the fault locating capability, by integrating OTM with the Power Supply Current (PSC) measurement technique. In PSC technique, the current passing through the VDD terminal is monitored during application of each input stimulus, wherein, every fault condition can be considered as a change in current through the VDD terminal. A fault is considered as detectable when the corresponding current value exceeds a tolerance bound around the nominal value. The sensitivity of the PSC measurement is investigated by considering those faults, which are indistinguishable, by no-oscillation in OTM. In order to test the feasibility of this technique, the threshold detector, which is commonly used in telephone tone ringer applications, was chosen for this study. In the initial test phase, OTM is applied to the detector circuit and the results showed that 129 faults were detectable, but the location was unidentifiable. In the second phase PSC measurement technique is applied in addition to the OTM to improve the fault locating capability. The results showed that 3 faults were uniquely identified and the remaining faults were grouped into 78 equivalent fault sets. Finally, in order to further increase the efficiency of the fault diagnostic resolution, a Node Voltage Measurement (NVM) technique was combined along with the above mentioned OTM and PSC techniques. In NVM measurement technique, voltage measurements were recorded at the output node of the individual op-amps and digital gates. Similar to PSC testing method, each measured node voltage has a tolerance band of+-5%. Since some faults within an equivalent fault set may cause different voltages to appear at different circuit nodes, these voltage amplitudes are then compared and used to further differentiate these faults within that particular equivalent fault set. Of the 126 faults unable to be located by the PSC technique, when tested by this method, the results showed that 44 faults were uniquely identified and the remaining were grouped into 122 equivalent fault sets. From the simulation experiment carried out, it is found that by coupling the OTM and PSC technique, only 8.24% of the fault location could be uniquely identified. Whereas, by integrating NVM based on a pre-selected set of internal circuit nodes, the diagnostic resolution could be increased by 26.35%. This thesis presents a detailed case study of the testing of a detector circuit using the OTM method and suggests solutions to enhance the fault diagnostic resolution. The difficulties and shortcomings of this testing approach are discussed in detail. In general, OTM is effective for its high fault coverage and is easy to implement. The major advantage over other testing approaches is that no test generation needs to be considered. The major weakness of OTM is the low identification capability of fault location. However, with careful selection of other parameters, such as power supply current measurement and node voltage measurements as carried out in this study, fault diagnostic resolution can be further improved|
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