| Author: | Qiao, Xuelong |
| Title: | FPGA based bit error rate tester |
| Degree: | M.Sc. |
| Year: | 2012 |
| Subject: | Error analysis (Mathematics) Data transmission systems -- Quality control. Field programmable gate arrays. Hong Kong Polytechnic University -- Dissertations |
| Department: | Department of Electronic and Information Engineering |
| Pages: | viii, 119 p. : ill. ; 30 cm. |
| Language: | English |
| Abstract: | Field Programmable Gate Array (FPGA) has been increasingly adopted as the mainstream technology for digital system design due to its programmability and easiness in system design. The dissertation describes the implementation of a Bit Error Rate Tester (BERT) based on Xilinx Spartan 3A FPGA board. The BERT consists of Transmitter, Receiver, and Comparator. The transmitter generates Pseudo-Random Binary Sequence (PRBS) inside the FPGA and feeds the sequence into a digital communication link under test. Receiver receives output signal from the communication receiver and provides synchronization function. The comparator compares the received signal with the original PRBS bitwise and counts errors. Spartan 3A Starter Kit from Xilinx is chosen for the implementation of the BERT system to simplify system development. Three case studies and design results are presented. |
| Rights: | All rights reserved |
| Access: | restricted access |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| b24757664.pdf | For All Users (off-campus access for PolyU Staff & Students only) | 2.14 MB | Adobe PDF | View/Open |
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