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dc.contributorDepartment of Electronic and Information Engineeringen_US
dc.creatorQiao, Xuelong-
dc.publisherHong Kong Polytechnic University-
dc.rightsAll rights reserveden_US
dc.titleFPGA based bit error rate testeren_US
dcterms.abstractField Programmable Gate Array (FPGA) has been increasingly adopted as the mainstream technology for digital system design due to its programmability and easiness in system design. The dissertation describes the implementation of a Bit Error Rate Tester (BERT) based on Xilinx Spartan 3A FPGA board. The BERT consists of Transmitter, Receiver, and Comparator. The transmitter generates Pseudo-Random Binary Sequence (PRBS) inside the FPGA and feeds the sequence into a digital communication link under test. Receiver receives output signal from the communication receiver and provides synchronization function. The comparator compares the received signal with the original PRBS bitwise and counts errors. Spartan 3A Starter Kit from Xilinx is chosen for the implementation of the BERT system to simplify system development. Three case studies and design results are presented.en_US
dcterms.extentviii, 119 p. : ill. ; 30 cm.en_US
dcterms.isPartOfPolyU Electronic Thesesen_US
dcterms.educationalLevelAll Masteren_US
dcterms.LCSHError analysis (Mathematics)en_US
dcterms.LCSHData transmission systems -- Quality control.en_US
dcterms.LCSHField programmable gate arrays.en_US
dcterms.LCSHHong Kong Polytechnic University -- Dissertationsen_US
dcterms.accessRightsrestricted accessen_US

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