|Title:||On abstraction methodologies for RTL-based VLSI designs to maximize high-level synthesis design space exploration and applications|
|Advisors:||Lau, Francis (EIE)|
Carrion Schafer, Benjamin (EIE)
|Subject:||Hong Kong Polytechnic University -- Dissertations|
Integrated circuits -- Design and construction
|Department:||Department of Electronic and Information Engineering|
|Pages:||xviii, 147 pages : illustrations|
|Abstract:||Moore's law has driven the complexity of Integrated Circuits (ICs) to unmanageable levels. To address this issue, extensive research is being done to develop new methodologies that can enable the design and verification of these complex ICs. In addition, current consumer trends are forcing IC design companies to continuously reduce the time-to-market while at the same time, the time-in-the-market of their products is shrinking, thus increasing significantly the risk of not obtaining the return-on-investment (ROI) targeted. One of the main design methodologies that helps addressing these issues is to re-use multiple components between different designs, as well as using third party intellectual properties (3PIPs). In addition, companies have started raising the level of VLSI design abstraction. From low-level Hardware Description Languages (HDLs), .e.g. Verilog and VHDL, to high-level languages (HLLs) that were originally designed for software (SW) development. High-Level Synthesis (HLS) enables the synthesis of these HLLs into efficient hardware that implements their behavior. HLS has multiple advantages over traditional HDL-based VLSI design. One of the advantages that this thesis studies extensively, is the ability to generate micro-architectures of unique characteristics (i.e. area, power, performance), without the need to modify the behavioral description. This is typically called Design Space Exploration (DSE). In particular, since most companies have large amounts of legacy Register Transfer Level (RTL) code, this thesis investigates automatic methods to convert these HDLs into HLL optimized for HLS, and in particular optimized for HLS DSE. The contributions of this thesis are multi-fold: First, this work proposes a robust translation framework which identifies patterns in RTL code (VHDL or Verilog) that translate into high-level constructs that can in turn be explored such that different unique micro-architectures are generated. These constructs mainly include loops, arrays and functions. Second, the work introduces an improved DSE system using a hybrid synthesis based predictive method. Third, the RTL abstraction framework is applied to accelerate cycle-accurate system-level simulations by generating fast behavioral templates. Finally, an open source synthesizable SystemC benchmark suite was released to study the effectiveness of the proposed methodology. Moreover, in three years the benchmark has grown from 13 designs to 18 and has reached over 100+ downloads.|
|Rights:||All rights reserved|
Files in This Item:
|991022164559503411.pdf||For All Users||2.58 MB||Adobe PDF||View/Open|
As a bona fide Library user, I declare that:
- I will abide by the rules and legal ordinances governing copyright regarding the use of the Database.
- I will use the Database for the purpose of my research or private study only and not for circulation or further reproduction or any other purpose.
- I agree to indemnify and hold the University harmless from and against any loss, damage, cost, liability or expenses arising from copyright infringement or unauthorized usage.
By downloading any item(s) listed above, you acknowledge that you have read and understood the copyright undertaking as stated above, and agree to be bound by all of its terms.
Please use this identifier to cite or link to this item: